There are three state-of-the art approaches for fabrication of ultra-thin semiconductor devices on silicon-on-insulator (SOI) substrates:    (1) The conventional process is fabrication without a raised source or drain. The thickness of silicon at the source/drain is the same as that of the channel region. This structure yields high source/drain parasitic resistance which degrades the device performance.    (2) In a channel thinning process, the SOI film at the channel region is thinned prior to gate oxidation. The disadvantage of this process is that the thinned SOI film region is extended out of the channel region by at least one lithography alignment tolerance. As a result the parasitic resistance in the channel region is large, and a high drive current cannot be obtained.    (3) In a raised source/drain process, after formation of the gate electrode and LDD ion implantation, an insulating sidewall is formed about the gate electrode. Silicon is selectively grown on the source/drain region and is silicided. The selective deposition of silicon or silicide has a relatively large pattern sensitive effect. That is the thickness of the selective deposition layer is thicker in the low density area and is thinner in the high density area. Therefore, the uniformity and reproducibility are poor.
Another method of fabricating an SOI transistor uses non-selective deposition of silicide, followed by CMP, etch back, and mask etching to remove unwanted silicide. The process has a set back of additional silicidation of silicon during post annealing or metal alloy process, which may consume too much silicon for ultrathin SOI film, causing voids, hence increasing the source/drain parasitic resistance.